Modern integrated circuits are integrating or embedding more and more memory on an integrated circuit die to meet functional and performance goals. The integration of large amounts of embedded memory is not limited to only complete and fabricated semiconductor devices. Design units known as embedded cores are also being provided with embedded memory, which are design descriptions that may be delivered as a behavioral, register transfer, or gate-level model, or may be delivered as a physical layout description. Any on-core memory becomes on-chip memory when the core is integrated into a complete semiconductor device.
In current art designs, embedded memory is generally placed along one side of the chip, or in one physical area. The embedded memory is then tested by one of several methods. One method of testing can be done by creating a test architecture that brings the data, address, and memory control lines (read/write, output enable, etc.) out to the chip interface during a memory test mode. This allows the tester to apply memory test algorithms directly to the memory as if the chip were a discrete memory chip. Another method of testing that can be used is an internal embedded Memory Built-In Self-Test (MBIST or memory BIST). In this case a single memory BIST controller creates the test stimulus and the test sequencing for all of the embedded memory arrays (the memory testing algorithms are embedded within the chip).
As process geometries (integrated circuit feature sizes) shrink, there is more opportunity and need to embed ever greater quantities of memory on single integrated circuit die. Another integration trend is the separation and distribution of memory arrays across a die, placing them near the functional units that they are associated with. One reason for this trend is the delivery of portions of the integrated circuit as core descriptions with separate embedded memories, with the embedded memory physically located with the delivered core unit. Another reason for this trend is that interconnect delay times are rapidly overcoming gate delay times.
However, the shrinking feature geometries and the large number of physically distributed memory arrays also creates even more test problems. For example, a direct access memory test architecture within a chip with a large number of distributed embedded memory arrays (e.g., 30 or more), and with memory arrays that have wide data paths (e.g., 32 or 64 bits), require a large amount of routing resources to allow the tester to have direct access to each of the memory arrays. This is compounded by the problem that in process geometries in the deep submicron range (below 0.5 micron), designs are more likely to be route limited, and routing becomes the greatest component in propagation timing delay. This architecture also requires a large number of borrowed functional pins to create the tester access pin interface, including the memory control interface which may include a "which memory to test" interface. Even though this architecture may be silicon and package costly in internal routes and borrowed package ins, it is "cost of tester memory" efficient since some automatic test equipment (ATE) can provide built-in algorithms to conduct memory test (very little tester memory is used for the storage of test program information). One of the negative trade-offs, in this case, is the lengthy test time required to test the memory arrays one at a time.
A similar set of trade-offs can be applied to a memory BIST architecture. In this case, the memory test sequencer, stimulus generator, and comparator logic are all embedded within a single chip. Access to all of the individual memory arrays is provided. This test architecture is still route intensive, but one main advantage is now that the MBIST functionality requires a much smaller package pin interface, consisting of (at a minimum): "invoke", "done", and "fail" signals, instead of having to supply the data bus, address bus, and read/write control signals as is required by a direct access test architecture. This is particularly advantageous for core design descriptions since in these architectures, a memory embedded within a core becomes "doubly embedded" when the core is embedded within a chip. The tester "cost of tester memory" is reasonably low in this type of testing, since MBIST can be run by having a tester subroutine that just "clocks" the chip until a "done" signal is asserted.
One of the key cost items to testing memories is a retention test. This test starts by loading sequential logic with a particular set of logic values (referred to as "DATA"), stopping the clock for a period of time, and then verifying the ability of the sequential logic to retain the first set of logic values. A second set of logic values, that are generally the complement of the first set ("DATABAR"), is then applied to the sequential logic, the clock is again stopped and re-started, and the sequential logic is verified again. This is a time costly test in relation to the length of the whole test program because of the two lengthy retention clock pauses described above.
The use of MBIST is more than just a methodology change for the memory test. It impacts the overall testing sequence for integrated circuits that involves scan testing, memory testing, memory retention testing, general sequential logic retention testing, and Iddq testing. For example, a prior art method of testing using a direct memory test access architecture generally conducts scan testing and memory testing as separate operations, but conducts a single chip-wide set of retention tests for scan and memory logic. Each memory array is loaded, that memory frozen, test mode changed, a scan state loaded, and then the pauses conducted. A test sequence like this typically breaks down into the following test program timetable (Table T-1):
TABLE T-1 ______________________________________ Test Types Test Times ______________________________________ Scan Tests 100ms Memory Tests (for at least 2 memories) 200ms per memory Scan Retention + Memory Retention 200ms per memory Iddq 100ms Total 1400ms+400ms/mem ______________________________________
A similar table (Table T-2) can be constructed for a single chip-level memory BIST controller. In this case, the scan tests and the memory tests are still done separately. Due to architectural limitations of applying an internal memory BIST controller made of system sequential elements, the scan and memory BIST cannot be operated simultaneously since the scan mode would disrupt the BIST controller. This means that the retention testing must now be done separately for scan logic and for memory logic. A single memory BIST controller can be designed to apply the memory test to all memory arrays simultaneously, so there is an overall test time saving in that all memory arrays can be tested simultaneously, and all memory arrays can be retention tested simultaneously.
TABLE T-2 ______________________________________ Test Types Test Times ______________________________________ Scan Tests 100ms Memory Tests (for at least 2 memories) 200ms all memory Scan Retention (4 pauses @ 50ms each) 200ms Memory Retention 200ms all memories Iddq 100ms DC Parametrics 400ms Total ______________________________________ 1200ms
From this point of view, the memory BIST method can be shown to be more effective than the direct access test method in test time. However, if the number of memory arrays included in the overall chip are large and they are widely distributed, then the negative trade-offs of routing, and potentially power consumption (testing all memory arrays simultaneously with an aggressive test algorithm may exceed the power rating of the chip or the package) may make manufactuability a risky prospect.